FIG. 1 shows charge transfer through a 4-phase charge-coupled device (CCD). The CCD consists of 4 gates V1, V2, V3, and V4 that control the flow of electrons through an n-type buried channel 105 in a p-type well 106 which is in an n-type substrate 107. At each time step T1 through T5 in FIG. 1, a channel potential diagram is drawn indicating where charge is located in the CCD. The voltages on the gate V1 through V4 at each time step are shown in FIG. 2. As charge moves through the CCD, there is no time at which the charge is held in an accumulated state. The accumulated state is when the gate voltage is low enough with respect to the p-type well or n-type substrate 107 to cause the accumulation of opposite electron charge carries (holes) at the surface of the buried channel 105. The accumulation of holes at the surface is well known to suppress dark current generation in CCDs. At all times in FIGS. 1 and 2, the charge packet is held under gates which are in the depleted state. The depleted state is when the gate voltage is high and prevents the accumulation of holes at the surface. That causes high dark current generation in the CCD and degrades quality of an image stored in the CCD.
FIG. 3 shows the clocking of charge through a similar CCD as FIG. 1. The difference being the presence of barrier implants 103 and 104 in the buried channel 102. The buried channel 102 is also built in a p-type well 100 on an n-type substrate 101. In this CCD, a different clocking scheme can used as shown in FIG. 4. At time T1 all of the CCD gates are at the low voltage level causing all gates to be accumulated with holes for low dark current. The barrier implants 103 and 104 keep the charge packet from flowing along the CCD. From times T2 through T6 the gates are clocked into the higher voltage depleted state for a short amount of time to advance the charge forward through the COD. Then at time T7, all gates are returned to the accumulated state for dark current suppression. By clocking the charge quickly between times T1 and T7 a minimal amount of dark current is added to the charge packet.
As disclosed by U.S. Pat. No. 6,586,784, the clock diagram in FIG. 4 has a shortcoming with uncompensated clock edges. Between times T1 and T2 gates V3 and V4 are both clocked with rising edges and no other clock has equal compensating falling edges. The gates V1 through V4 have a capacitance with the p-type well 100. If there are an equal number of rising edges as there are falling edges then the capacitive coupling of the gates V1 through V4 to the p-type well 100 are cancelled out. But the rising edges of the V3 and V4 gate timing of FIG. 4 between times T1 and T2 are not cancelled out. This will cause the p-type well 100 voltage to ‘bounce’ and cause poor charge transfer or even loss of charge in the CCD.
U.S. Pat. No. 6,585,784 solves the p-well bounce problem by clocking the gates V1 through V4 with three voltage levels as shown in FIG. 5. The voltage levels and timing are chosen such that
            ∑      n        ⁢                  C        n            ⁢      Δ      ⁢                          ⁢              V        n              ≅  0.Cn is the capacitance of gate n to the p-type well 100, and ΔVn is the change in clock voltage on gate n, where n is the number 1 through 4 corresponding to gates V1 through V4. The problem with this three level voltage solution is how to create a clock driver that outputs three voltage levels. It can be done with discrete electronic components, but they are costly compared to integrated circuit clock drivers. However, the integrated circuit clock drivers available can only generate two voltage levels, not the required three levels.
The present invention described herein will allow for low dark current clocking of a CCD with no p-well bounce while only requiring two voltage level clock drivers. The present invention enables the use of inexpensive integrated clock drivers for low dark current CCD clocking.